4-layer 3-D IC technologies for parallel signal processing

@article{Yamazaki19904layer3I,
  title={4-layer 3-D IC technologies for parallel signal processing},
  author={K. Yamazaki and Y. Itoh and A. Wada and K. Morimoto and Y. Tomita},
  journal={International Technical Digest on Electron Devices},
  year={1990},
  pages={599-602}
}
  • K. Yamazaki, Y. Itoh, +2 authors Y. Tomita
  • Published 1990
  • Physics
  • International Technical Digest on Electron Devices
  • A four-layer 3-D device used for parallel image signal processing was fabricated as an example of a primitive 3-D device. SOI (silicon-on-insulator) layers were formed by laser recrystallization. Mesa-type transistors having a stacked dielectric gate insulator were fabricated in a laser recrystallized Si island array. Thermally stable interconnections and contacts were realized by TiSi/sub x/ wiring and TiSi/sub x//TiN/TiSi/sub 2//Si-sub. contact structure. For the interlayer connections, a… CONTINUE READING
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