4-layer 3-D IC technologies for parallel signal processing

@article{Yamazaki19904layer3I,
  title={4-layer 3-D IC technologies for parallel signal processing},
  author={K. Yamazaki and Y. Itoh and A. Wada and K. Morimoto and Y. Tomita},
  journal={International Technical Digest on Electron Devices},
  year={1990},
  pages={599-602}
}
A four-layer 3-D device used for parallel image signal processing was fabricated as an example of a primitive 3-D device. SOI (silicon-on-insulator) layers were formed by laser recrystallization. Mesa-type transistors having a stacked dielectric gate insulator were fabricated in a laser recrystallized Si island array. Thermally stable interconnections and contacts were realized by TiSi/sub x/ wiring and TiSi/sub x//TiN/TiSi/sub 2//Si-sub. contact structure. For the interlayer connections, a… 
View on IEEE
doi.org
19 Citations
Highly Influential Citations
1
Background Citations
3
Methods Citations
1

Figures from this paper

19 Citations

Citation Type

Citation Type

Three-dimensional integration: technology, use, and issues for mixed-signal applications
Three-dimensional (3-D) integration provides opportunities in large-scale integration of mixed-signal and general system-on-chip applications with improved performance, through increased density and…
Trend and Prospect for 3Dimensional Integrated-Circuit Semiconductor Chip
As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the…
4-Layer 3-D IC with a function of parallel signal processing
New Excimer Laser Annealing Process for Single-Crystal 3-D Stacked Thin-Film Transistors
Since the concept of 3-D ICs was introduced about twenty years ago [1-6], considerable attention has been paid to 3-D ICs fabrication with silicon-oninsulator (SOI) technology because it enables high…
3D integrated circuit using large grain polysilicon film
  • V.W.C. Chan, P. Chan, M. Chan
  • Materials Science
    2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)
  • 2001
3-D CMOS IC technology built on two layers of large grain polysilicon is presented. These stacked layers are vertically interconnected allowing shorter interconnect to improve the logic speed. The…
Three dimensional CMOS integrated circuits on large grain polysilicon films
  • V.W.C. Chan, P. Chan, M. Chan
  • Engineering
    International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
  • 2000
In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated…
Silicon on insulator-an emerging high-leverage technology
Silicon on insulator (SOI) has emerged as a high-leverage technology for a wide range of commercial and military applications. While the use of SOI is presently limited to special niche applications,…
Silicon on insulator-an emerging high-leverage technology
TLDR
The status of SOI material is discussed, including the different methods used to prepare large SOI wafers, wafer availability, cost reduction strategies, material characterization, and material quality.
3D heterogeneous sensor system on a chip for defense and security applications
TLDR
A unique approach is discussed, namely a 3-D Heterogeneous System on a Chip (HSoC) in order to achieve a minimum 10X reduction in weight, volume, and power and a 10X or greater increase in capability and reliability -- over the alternative planar approaches.
Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET
Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked…
...
1
2
...

References

SHOWING 1-2 OF 2 REFERENCES
Purposes of three-dimensional circuits
TLDR
The authors attempt to identify the principal advantages of 3-D circuitry, the types of circuits that will best provide these advantages, and the technology problems that should be given priority.
Extended Abstracts
Tummala & Sathe used incorrect concepts in investi-gating properties of estimators and drew incorrect conclusions.