4-Mb MOSFET-selected phase-change memory experimental chip

  title={4-Mb MOSFET-selected phase-change memory experimental chip},
  author={Ferdinando Bedeschi and R. Bez and Chiara Boffino and Edoardo Bonizzoni and E. Buda and Giulio Casagrande and Lu{\'i}s Costa and Mena Ferraro and Roberto Gastaldi and Osama Khouri and François-Ga{\"e}l Ottogalli and F. Pellizzer and A. Pirovano and Claudio Resta and Guido Torelli and Milorad To{\vs}i},
  journal={Proceedings of the 30th European Solid-State Circuits Conference},
This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell… CONTINUE READING
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