3D stacking induced mechanical stress effects

@article{Cherman20143DSI,
  title={3D stacking induced mechanical stress effects},
  author={Vladimir Cherman and Geert Van der Plas and Joeri De Vos and Andrej Ivankovic and Melina Lofrano and Veerle Simons and M. B. Gonz{\'a}lez and Kris Vanstreels and Teng Wang and Robert Daily and Wei Guo and Gerald P. Beyer and Antonio la Manna and Ingrid De Wolf and Eric Beyne},
  journal={2014 IEEE 64th Electronic Components and Technology Conference (ECTC)},
  year={2014},
  pages={309-315}
}
In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements. 
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