3D integration technology and reliability

@article{Koyanagi20113DIT,
  title={3D integration technology and reliability},
  author={Mitsumasa Koyanagi},
  journal={2011 International Reliability Physics Symposium},
  year={2011},
  pages={3F.1.1-3F.1.7}
}
Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20µm induced the maximum compressive stress of ∼1 GPa at the silicon substrate adjacent to them after annealed at 300°C for 30 min. Mechanical strain/stress… CONTINUE READING

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Comprehensive Analysis of the Impact of Single and Arrays of Through Silicon Vias Induced Stress on High-k / Metal Gate CMOS Performance,

  • A. Mercha
  • Int. Electron Devices Meeting (IEDM) Dig.,
  • 2010
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