• Corpus ID: 62780117

3D Integration Technology and Heterogeneous Integration

@inproceedings{Koyanagi20113DIT,
  title={3D Integration Technology and Heterogeneous Integration},
  author={Mitsumasa Koyanagi and Takafumi Fukushima and Kang-wook Lee and Tetsu Tanaka},
  year={2011}
}
あらまし これまで,LSI は,半導体素子の微細化により,著しい速度で高性能化,大容量化が達成されてき た.しかし,消費電力の増大や特性ばらつきの増加などにより微細化が次第に難しくなってきている.これらの 問題を解決するためには,素子の微細化だけでなく,LSI に実装技術や MEMS 技術,フォトニクス技術などの 異種技術を融合して,システム全体で高性能化,高機能化を図る新しい集積化技術が必要となる.したがって, 今後の LSI 開発は,素子の微細化を更に進める More Moore 技術と,異種技術を融合する More than Moore 技術を車の両輪のようにうまく協調,共存させながら進めていくことが重要になる.本論文では,More than Moore技術を代表する技術の一つである三次元集積化技術とヘテロインテグレーション技術について,現状の課 題と将来の可能性について言及する. キーワード 三次元 LSI,シリコン貫通配線(TSV),マイクロバンプ,セルフアセンブリー,ヘテロインテ グレーション 
search.ieice.org
1 Citations

One Citation

Citation Type

Citation Type

High Speep/High-Precision Chip Joining Using Self-Assembly Technology for Three-Dimensional Integrated Circuits
Moore의 법칙으로 알려져 있듯이, 지금까지 LSI는 미세가공기술의 진보에 따른 반도체소자의 미세화를 통해 2-3년에 4배라는 놀라운 속도로 고성능화, 대용량화가 달성되어져 왔다. 그러나 반도체 소자의 미세화가 11 nm node 이하로 진행됨에 따른 누설전류(Leakage Current)의 증가, 특성 불균형의 증가, 소비전력의 증대 및 노광장치등의…

References

SHOWING 1-10 OF 51 REFERENCES
InterChip via technology for vertical system integration
  • P. Ramm, D. Bonfert, R. Wieland
  • Engineering
    Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)
  • 2001
Vertical System Integration VSI(R) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested…
High-Density Through Silicon Vias for 3-D LSIs
TLDR
The 3-D microprocessor test chip,3-D memorytest chip, 3- D image sensor chip, and 3-Ds artificial retina chip were successfully fabricated by using poly-Si TSV and tungsten (W/poly-Si) TSV technology.
3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)
We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel…
Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems
TLDR
The basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology.
New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique
We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the…
Future system-on-silicon LSI chips
TLDR
In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
3D stacked IC demonstration using a through Silicon Via First approach
We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of…
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method.…
Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method
We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of…
Neuromorphic vision chip fabricated using three-dimensional integration technology
  • M. Koyanagi, Y. Nakagawa, H. Kurino
  • Biology
    2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
  • 2001
TLDR
The three-dimensional (3D) integration technology reported here achieves an image processing and pattern recognition system with parts of functions of the retina and visual cortex using silicon.
...
1
2
3
4
5
...