3D FPGAs: placement, routing, and architecture evaluation (abstract only)

@inproceedings{Ababei20053DFP,
  title={3D FPGAs: placement, routing, and architecture evaluation (abstract only)},
  author={Cristinel Ababei and Hushrav Mogal and Kia Bazargan},
  booktitle={FPGA},
  year={2005}
}
This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS… CONTINUE READING