340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

@article{Mathew2015340MV,
  title={340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS},
  author={Sanu K. Mathew and Sudhir Satpathy and Vikram Suresh and Mark Anders and Himanshu Kaul and Amit Agarwal and Steven Hsu and Gregory K. Chen and Ram Krishnamurthy},
  journal={IEEE Journal of Solid-State Circuits},
  year={2015},
  volume={50},
  pages={1048-1058}
}
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native GF(24)2 composite-field. This approach along with a serial-accumulating MixColumns circuit, area… CONTINUE READING
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340 mV–1.1 V, 289 Gbps/W, 2090-gate nanoAES hardware accelerator with area-optimized encrypt/ decrypt polynomials in 22 nm tri-gate CMOS

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