32nm high-density high-speed T-RAM embedded memory technology

@article{Gupta201032nmHH,
  title={32nm high-density high-speed T-RAM embedded memory technology},
  author={Rajesh Gupta and Farid Nemati and Scott Robins and K. Jian Yang and Vasudevan Gopalakrishnan and Joseph John Sundarraj and Rajesh Chopra and Rich Roy and Hyun-jin Cho and W. P. Maszara and Nihar Ranjan Mohapatra and John Wuu and Don Weiss and Sam Nakib},
  journal={2010 International Electron Devices Meeting},
  year={2010},
  pages={12.1.1-12.1.4}
}
Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time. T-RAM memory cell median read current of 250µA/cell at 1.2V with an Ion/Ioff current ratio of more than 108 is demonstrated at 105°C. Robust margins… CONTINUE READING
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