32-bit cyclic redundancy codes for Internet applications

@article{Koopman200232bitCR,
  title={32-bit cyclic redundancy codes for Internet applications},
  author={Philip Koopman},
  journal={Proceedings International Conference on Dependable Systems and Networks},
  year={2002},
  pages={459-468}
}
  • P. Koopman
  • Published 23 June 2002
  • Computer Science
  • Proceedings International Conference on Dependable Systems and Networks
Standardized 32-bit cyclic redundancy codes provide fewer bits of guaranteed error detection than they could, achieving a Hamming Distance (HD) of only 4 for maximum-length Ethernet messages, whereas HD=6 is possible. Although research has revealed improved codes, exploring the entire design space has previously been computationally intractable, even for special-purpose hardware. Moreover, no CRC polynomial has yet been found that satisfies an emerging need to attain both HD=6 for 12K bit… 

Figures and Tables from this paper

Efficient High Hamming Distance CRCs for Embedded Networks

  • Justin RayP. Koopman
  • Computer Science
    International Conference on Dependable Systems and Networks (DSN'06)
  • 2006
This work evaluates the options for speeding up CRC computations on 8-bit processors, including comparing variants of table lookup approaches for memory cost and speed and recommends classes of CRC generator polynomials which have the same computational cost as 24- or 16-bit CRCs, but provide 32- bit CRC levels of error detection.

Cyclic redundancy code (CRC) polynomial selection for embedded networks

A polynomial selection process for embedded network applications is described and a set of good general-purpose polynomials are proposed that provide good performance for 3- to 16-bit CRCs for data word lengths up to 2048 bits.

Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol

A novel model which can be used to investigate several classes of CRC polynomials codes with ‘n’ parity bits varying from ‘1’ to ‘64’ is presented, which is proposed to search good CRC codes of 32, 40 and 64 bit and studying performance for maximum payload over Ethernet protocol.

Development of a reduction algorithm for CAN frame bits

This paper proposes a different error correction technique which is called as the Enhanced-Error Detection (EED) code and aims to increase the CAN's frame rate and can be a better option for detecting and correcting the error in CAN System.

FPGA implementation of hamming code for increasing the frame rate of CAN communication

The main objective of this algorithm is to use an alternative error correction scheme called as the Hamming code, replacing the conventional CRC code, to possibly increase the CAN's frame rate of the system.

Implementation of an Enhanced-Hamming Code Method for CAN Communication to Reduce the Frame Bits

This proposal uses an enhanced-Hamming code, because the redundancy bits will be appended at the end of the data bits to possibly increase the CAN's frame rate of the system and to avoid in using the overhead payload of spreading these bits.

Error control with binary cyclic codes

It can be shown that the correction of a single-bit error on the basis of a cyclic code is equivalent to the solution of an instance of the discrete logarithm problem, leading to a deterministic algorithm for small group orders that has linear space and linearithmic time requirements in the degree of defining polynomial.

Coverage and the use of cyclic redundancy codes in ultra-dependable systems

This paper identifies some examples of CRC usage that compromise ultra-dependable system design goals, and recommends alternate ways to improve system dependability via architectural approaches rather than error detection coding approaches.

Cooperative communication system with systematic Raptor codes

  • Ding WangM. Soleymani
  • Computer Science
    2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)
  • 2012
This paper proposes a relay scheme using systematic Raptor code which is standardized in 3GPP, and develops ways of optimizing the system with channel state information at the transmitter, including adaptive RS coding rates and adaptive cooperation of relay.
...

References

SHOWING 1-10 OF 17 REFERENCES

Optimization of cyclic redundancy-check codes with 24 and 32 parity bits

Using this method implemented on a high-speed special-purpose processor, several classes of cyclic redundancy-check (CRC) codes with 24 and 32 parity bits are investigated and the d/sub min/ profiles of the resulting codes are presented and compared with recent suggestions.

On the Undetected Error Probability for Shortened Hamming Codes

It is shown that shortening a code does affect its error-detection performance, and the two distance-4 Hamming codes adopted by CCITT X for error control for packet-switched networks are affected.

Error control coding

The basic goal in digital communications is to transport bits of information without losing too much information along the way. The level of information loss that is tolerable/acceptable varies for

When the CRC and TCP checksum disagree

The highly non-random distribution of errors strongly suggests some applications should employ application-level checksums or equivalents, and proposes simple changes to several protocols which will decrease the rate of undetected error.

Applied Coding and Information Theory for Engineers

This chapter discusses Shannon's Coding Theorems, which describe the construction of codes based on discrete sources and entropy, and their applications in information theory and Cryptography.

iSCSI

  • Internet-Draft work in progress, http://www.ietf.org/internet-drafts/draft-ietf-ips-iscsi -08.txt, Sept. 30 2001, accessed Nov. 10,
  • 2001

Error-Correcting Codes

iSCSI CRC/Checksum Considerations Internet-Draft work in progress, http://search. ietf.org/internet-drafts/draft-sheinwald-iscsi-crc-00.txt

  • iSCSI CRC/Checksum Considerations Internet-Draft work in progress, http://search. ietf.org/internet-drafts/draft-sheinwald-iscsi-crc-00.txt
  • 2001

IP Storage (ips) Charter

  • IP Storage (ips) Charter
  • 2001

Acknowledgments Significant use was made of equipment donated by Digital Equipment Corporation (now Compaq). Additional equipment support was provided by Intel

  • Acknowledgments Significant use was made of equipment donated by Digital Equipment Corporation (now Compaq). Additional equipment support was provided by Intel