3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS

@article{Choi201538A0,
  title={3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS},
  author={Woo-Seok Choi and Guanghua Shu and Mrunmay Talegaonkar and Yubo Liu and Da Wei and Luca Benini and Pavan Kumar Hanumolu},
  journal={2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers},
  year={2015},
  pages={1-3}
}
Supply voltage (VDD) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower… CONTINUE READING

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