Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization
Modern mobile device possesses function-rich, small, thin, low-power features. The electronics industry aggressively seeks possible solutions to achieve these demands. Among different techniques, 3-D integration can effectively provide such kind of advantages. However, to successfully accomplish vertical stacking, readiness of design toolset is one of the most important keys. In this paper, we present the challenges and state-of-the-art features of 3-D EDA tool chain. We introduce the complete realization technologies of system integration with through-silicon via (TSV) using TSMC 90nm process. For optimization of system performance, we summarize the stacking concerns for timing constraints due to various stacking applications. With the configurations, an approach is proposed to overcome 3-D timing optimization problem because commercial tool tackles only one die at one time. Empirical results show the approach is promising for present 3-D centric design methodologies.