3-D ICs : A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration

@inproceedings{Banerjee20013DI,
  title={3-D ICs : A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration},
  author={Kaustav Banerjee and Pawan Kapur},
  year={2001}
}
Performance of deep submicron VLSI is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel 3-dimensional (3-D) chip design strategy that exploits the… CONTINUE READING
Highly Influential
This paper has highly influenced 47 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 683 citations. REVIEW CITATIONS
458 Citations
123 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 458 extracted citations

683 Citations

050'01'04'08'12'16
Citations per Year
Semantic Scholar estimates that this publication has 683 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 123 references

Similar Papers

Loading similar papers…