3-D ICs : A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration

@inproceedings{Banerjee20013DI,
  title={3-D ICs : A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration},
  author={Kaustav Banerjee and Pawan Kapur},
  year={2001}
}
Performance of deep submicron VLSI is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel 3-dimensional (3-D) chip design strategy that exploits the… CONTINUE READING
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