26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection

@article{Floyd2017265AC,
  title={26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection},
  author={Michael S. Floyd and Phillip Restle and Michael A. Sperling and Pawel Owczarczyk and Eric Fluhr and Joshua Friedrich and Paul Muench and Tim Diemoz and Pierce Chuang and Christos Vezyrtzis},
  journal={2017 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2017},
  pages={444-445}
}
Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (VDD) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked loop (DPLL) to immediately reduce clock frequency in response. 

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