26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS

@article{Chan2015265A5,
  title={26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS},
  author={C. Chan and Yan Zhu and Sai-Weng Sin and U. Seng-Pan and R. Martins},
  journal={2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers},
  year={2015},
  pages={1-3}
}
  • C. Chan, Yan Zhu, +2 authors R. Martins
  • Published 2015
  • Computer Science, Engineering
  • 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
Communication devices such as 60GHz-band receivers and serial links demand power-efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of ADCs is degraded by scaling up transistor widths in the building blocks for high speed, thus increasing the impact of intrinsic parasitics. Parallel schemes like multi-bit processing and interleaving [1], can ease the problems caused by scaling and lead to better efficiency if the hardware overhead is wisely reduced [2]. This… Expand
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References

SHOWING 1-3 OF 3 REFERENCES
An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI
  • 36
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS
  • 59
  • PDF
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators
  • Yun-Shiang Shu
  • Computer Science
  • 2012 Symposium on VLSI Circuits (VLSIC)
  • 2012
  • 77