26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

@article{Jaussi2014262A2,
  title={26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS},
  author={James E. Jaussi and Ganesh Balamurugan and Sami Hyvonen and Tzu-Chien Hsueh and Tawfiq Musah and Gokce Keskin and Sudip Shekhar and Joseph Kennedy and Shreyas Sen and Rajesh Inti and Mozhgan Mansuri and Michael Leddige and Bryce Horine and Clark Roberts and Randy Mooney and Bryan Casper},
  journal={2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
  year={2014},
  pages={440-441}
}
Peripheral I/O data-rates for PCs and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays and large-capacity external storage. The bandwidth requirements will soon exceed the data-rates of current standards such as PCI Express and USB. A low-power low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1-2]. However, the… CONTINUE READING