250 MHz Multiphase Delay Locked Loop for Low Power Applications

Received Mar 17, 2017 Revised Sep 8, 2017 Accepted Sep 20, 2017 Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL… CONTINUE READING