25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

@article{Lee2014252A1,
  title={25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV},
  author={Dong Uk Lee and Kyung Whan Kim and Kwan Weon Kim and Hongjung Kim and Ju Young Kim and Young Jun Park and Jae Hwan Kim and Dae Suk Kim and Heat Bit Park and Jinkin Shin and Jang Hwan Cho and Ki Hun Kwon and Min Jeong Kim and Jaejin Lee and Kun Woo Park and Byong-Tae Chung and Sungjoo Hong},
  journal={2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
  year={2014},
  pages={432-433}
}
  • Dong Uk Lee, Kyung Whan Kim, +14 authors S. Hong
  • Published 6 March 2014
  • Engineering, Computer Science
  • 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high… Expand
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