24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm

@article{Lee2016242A2,
  title={24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm},
  author={Edward H. Lee and S. Simon Wong},
  journal={2016 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2016},
  pages={418-419}
}
Matrix multiplication, enabled by multiply-and-accumulate hardware, is ubiquitous in signal processing, computer graphics, machine learning, and optimization. Many important applications with inherent robustness to reduced precision for matrix multiplication, e.g. inference for neural networks [1], can take advantage of analog signal processing for energy efficiency. This work presents a 64-cycle programmable passive Switched-Capacitor Matrix Multiplier (SCMM) with co-designed bitline-less… CONTINUE READING

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