21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise

@article{Huang2014212A2,
  title={21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise},
  author={Po-Chun Huang and Wei-Sung Chang and Tai-Cheng Lee},
  journal={2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
  year={2014},
  pages={362-363}
}
Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these dividerless architectures can only be operated in integer-N mode inherently. In order to operate in fractional-N mode, this work proposes a digital pulse-width modulator (DPWM) to modulate the pulse width of the input reference signal to synthesize the output frequency. 
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