21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC

@article{Marucci2014211A1,
  title={21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC},
  author={Giovanni Marucci and Andrea Fenaroli and Giovanni Marzin and Salvatore Levantino and Carlo Samori and Andrea L. Lacaita},
  journal={2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
  year={2014},
  pages={360-361}
}
The introduction of inductorless frequency synthesizers into standardized wireless systems still requires a high level of innovation in order to achieve the stringent requirements of low noise and low power consumption. Synthesizers based on the so-called multiplying delay-locked loop (MDLL) represent one of the most promising architectures in this direction [1-3]. An MDLL resembles a ring oscillator, in which the signal edge traveling along the delay line is periodically refreshed by a clean… CONTINUE READING
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