21-Layer 3-D Chip Stacking Based on Cu-Sn Bump Bonding

@article{Li201521Layer3C,
  title={21-Layer 3-D Chip Stacking Based on Cu-Sn Bump Bonding},
  author={Cao Li and Xuefang Wang and Shao Yun Song and Sheng Liu},
  journal={IEEE Transactions on Components, Packaging and Manufacturing Technology},
  year={2015},
  volume={5},
  pages={627-635}
}
A 3-D chip-to-chip stacking technology is presented, in which several key techniques involving the wafer thinning process are integrated, through silicon via (TSV) etching and plating, redistribution layer formulation, and the flip chip chip bonding process. Nanoporous Cu-Sn microbump bonding technology is introduced, and a novel 3-D module-to-module bonding method is developed. Compared with the reported 3-D packaging technologies, a chip stacking module with more than 21 layers is obtained in… CONTINUE READING

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