Integrated buck VR designs with different types of power inductor integration technologies have been reported [1-3]. In , planar lateral coupled power inductors with non-planar magnetic cores for higher inductance, quality factor and current density, are integrated on a separate silicon interposer die which is then wirebonded to the VR die on a common BGA laminate. While an interposer die for inductor integration enables small inductor footprint, parasitic impedances of the wirebonds degrade inductor quality, overall VR performance and efficiency. In addition, the total thickness (z-height) of the packaged two-die stack is too large for ultra-thin form factor systems. High quality-factor air-core power inductors are integrated within the package layers in , utilizing the thick package core. However, they are difficult to integrate in ultra-thin coreless packages with few package layers. Also, scalability of the inductor footprint to fine domains is limited. Furthermore, since the inductors cannot be co-located with the SoC DVFS domains for both of these inductor integration options, scalability to finer domains is curtailed. Planar lateral spiral inductors without magnetics are integrated directly on the VR die in , utilizing upper metal layers. Although this option is suitable for realizing ultra-thin packaged dies and the inductor footprint can be scaled to finer domains, the quality factor and inductance density are too low to support high current density needed for viable on-die power conversion.