2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications

Abstract

A 2.8 to 67.2 mW H.264 encoder is implemented on a 12.8 mm<sup>2</sup> die with 0.18 mum CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock. 

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Cite this paper

@article{Chen200728T6, title={2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications}, author={Tung-Chien Chen and Yu-Han Chen and Chuan-Yung Tsai and Sung-Fang Tsai and Shao-Yi Chien and Liang-Gee Chen}, journal={2007 IEEE Symposium on VLSI Circuits}, year={2007}, pages={222-223} }