2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

@article{Kimura20142125,
  title={2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS},
  author={H. Kimura and Pervez M. Aziz and Tai Jing and Ashutosh Sinha and Ram Narayan and Hairong Gao and Ping Jing and Gary Hom and Anshi Liang and Eric Zhang and Aniket Kadkol and Ruchi Kothari and Gordon Chan and Yehui Sun and Benjamin Ge and Jason Zeng and Kathy Ling and Michael C. Wang and Amaresh V. Malipatil and Shiva Kotagiri and Lijun Li and Chris Abel and Freeman Zhong},
  journal={2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
  year={2014},
  pages={38-39}
}
A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important… CONTINUE READING
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