18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

@article{Ramanarayanan201018Gbps5R,
  title={18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS},
  author={Rajaraman Ramanarayanan and Sanu K. Mathew and Farhana Sheikh and Suresh Srinivasan and Amit Agarwal and Steven Hsu and Himanshu Kaul and Mark Anders and Vasantha Erraguntla and Ram Krishnamurthy},
  journal={2010 Proceedings of ESSCIRC},
  year={2010},
  pages={210-213}
}
A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across… CONTINUE READING