17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI

@article{Khayatzadeh2016173AR,
  title={17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI},
  author={Mahmood Khayatzadeh and Mehdi Saligane and Jingcheng Wang and Massimo Alioto and David Blaauw and Dennis Sylvester},
  journal={2016 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2016},
  pages={310-312}
}
SRAM is a key building block in systems-on-chip and usually limits their voltage scalability, due to the major impact of process/voltage/temperature (PVT) variations at low voltages [1]. Assist techniques to extend SRAM operating voltage range improve the bit cell read/write stability [1-5], but cannot mitigate variations in the internal sensing delay that is needed to develop the targeted bitline (BL) voltage. Hence, large guard bands and performance margins are still needed to ensure correct… CONTINUE READING

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