16nm with 193nm immersion lithography and double exposure

  title={16nm with 193nm immersion lithography and double exposure},
  author={V. Axelrad and M. Smayling},
  booktitle={Advanced Lithography},
Gridded Design Rules (GDR) in combination with lines/ cuts double patterning allow imaging of 16nm designs with 193nm immersion lithography. Highly regular lines/ cut patterns result in the existence of a well-defined optimal set of lithographic conditions. Since cuts are all of identical shape and relatively sparse, good image quality can be obtained with minimal or simplified pattern correction (OPC equivalent) to compensate for proximity effects. The use of local interconnect (LI) is shown… Expand
Optical lithography applied to 20-nm CMOS Logic and SRAM
This work extends on earlier results to show simulation-based patterning of both SRAMs and logic cells, consistent with the emerging industry consensus that regular designs and multiple exposure techniques will extend 193nm immersion as far down as 7nm. Expand
Sub-12nm optical lithography with 4x pitch division and SMO-lite
The scaling using SMO with simplified OPC is extended in a technique called “SMOLite” beyond 16nm, with the same “cut” pattern used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. Expand
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design
This paper proposes a novel algorithm to optimally assign cuts to 193i or E-Beam processes with proper modifications on cut distribution in order to maximize the overall throughput and shows that the throughput is dramatically improved by the cut redistribution. Expand
Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization
It proves that complex patterns with many fragments make MEEF higher and co-optimization and insertion of SRAF works very well considering the appropriate printed shape required by the device layout. Expand
Sub-20nm logic lithography optimization with simple OPC and multiple pitch division
The scaling using simplified OPC beyond 20nm in small steps is extended, eventually reaching the 16nm node and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF. Expand
Improvement of lithographic performance and reduction of mask cost by simple OPC
An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be competitive to a solution by complicated source shape and mask pattern. This technologyExpand
Custom source and mask optimization for 20nm SRAM and logic
This work considers a design with the logic and SRAMs unified from the beginning, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches, and truly optimizes both. Expand
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs
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Layout optimization through robust pattern learning and prediction in SADP gridded designs
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Photon and Electron Induced Macromolecular Synthesis on Insulating Surfaces
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Simulation-Based Lithography Optimization for Logic Circuits at 22nm and Below
  • M. Smayling, V. Axelrad
  • Physics
  • 2009 International Conference on Simulation of Semiconductor Processes and Devices
  • 2009
Lithography optimization based on physical simulation is a powerful technique to achieve good image quality at subwavelength feature sizes with small Rayleigh k1 factors. For the lower end of theExpand
32nm and below logic patterning using optimized illumination and double patterning
Line/space dimensions for 32nm generation logic are expected to be ~45-50nm at ~90-100nm pitch. It is likely that the node will begin at the upper end of the range, and then shrink by ~10% to aExpand
High-throughput hybrid optical maskless lithography: all-optical 32-nm node imaging
We analyze the performance and process latitudes of a high-throughput, all-optical lithography method that addresses the requirements of the 32-nm node. This hybrid scheme involves a double exposureExpand
Lithography 2009: Overview of Opportunities,
  • Semicon West,
  • 2009
Smayling, “Gridded Design Rules – 1-D Design Enables Scaling of CMOS Logic,
  • Nanochip Technology Journal,
  • 2008
All-Optical 32-nm Node Imaging,” Proc
  • of SPIE, vol. 5751,
  • 2005
Gridded Design Rules – 1 - D Design Enables Scaling of CMOS Logic
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