15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS

@article{Elkholy2014154A2,
  title={15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS},
  author={Ahmed Elkholy and Amr Elshazly and Saurabh Saxena and Guanghua Shu and Pavan Kumar Hanumolu},
  journal={2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)},
  year={2014},
  pages={272-273}
}
Modern systems-on-chips (SoCs) perform many diverse analog, digital, and mixed-signal functions. They contain a wide variety of modules such as multicore processors, memories, I/O interfaces, power management, and wireless transceivers. Each module has its own unique clock requirements to maximize the overall system performance. For example, dynamic frequency scaling (DFS) saves processor power, spread spectrum clocking (SSC) reduces electromagnetic interference (EMI), and rapid power cycling… CONTINUE READING
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