14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

@article{Deng2015141A0,
  title={14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique},
  author={Wei Deng and Dongsheng Yang and Aravind Tharayil Narayanan and Kengo Nakata and Teerachot Siriburanon and Kenichi Okada and Akira Matsuzawa},
  journal={2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers},
  year={2015},
  pages={1-3}
}
Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed to reduce the design cost and allow easier integration. To achieve high-frequency resolution, PLLs are required to operate in fractional-N mode, in addition to integer-N mode. There are several architectures… CONTINUE READING

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