13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications

@article{Madoglio2017136A2,
  title={13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications},
  author={Paolo Madoglio and Hongtao Xu and Kailash Chandrashekar and Luis Cuellar and Muhammad Faisal and Yee William Li and Hyung Seok Kim and Khoa Minh Nguyen and Yulin Tan and Brent R. Carlton and Vaibhav A. Vaidya and Yanjie Wang and Thomas Tetzlaff and Satoshi Suzuki and Amr Fahim and Parmoon Seddighrad and Jianyong Xie and Zhichao Zhang and Divya Shree Vemparala and Ashoke Ravi and Stefano Pellerano and Yorgos Palaskas},
  journal={2017 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2017},
  pages={226-227}
}
To benefit from Moore's law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are required, increasing system cost and form-factor. Traditional radio architectures require extensive use of high-quality passives, which might use large silicon area or not be available due to process limitations. Fast time to market also demands… CONTINUE READING
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