120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

@article{Yang2015120VnsOS,
  title={120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs},
  author={Hsiang-An Yang and Chao-Chang Chiu and Shin-Chi Lai and Jui-Lung Chen and Chih-Wei Chang and Che-Hao Meng and Ke-Horng Chen and Chin-Long Wey and Ying-Hsi Lin and Chao-Cheng Lee and Jian-Ru Lin and Tsung-Yen Tsai and Hsin-Yu Luo},
  journal={ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)},
  year={2015},
  pages={291-294}
}
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a… CONTINUE READING