11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

  title={11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory},
  author={Chulbum Kim and Ji-Ho Cho and Woopyo Jeong and Il Han Park and Hyun-wook Park and Doo-Hyun Kim and Daewoong Kang and Sunghoon Lee and Ji-Sang Lee and Won-tae Kim and Jiyoon Park and Yang-Lo Ahn and Jiyoung Lee and Jong-Hoon Lee and Seungbum Kim and Hyun-Jun Yoon and Jaedoeg Yu and Nayoung Choi and Yelim Kwon and Nahyun Kim and Hwajun Jang and Jonghoon Park and Seunghwan Song and Yongha Park and Jinbae Bang and Sangki Hong and Byung Hoon Jeong and Hyun-Jin Kim and Chunan Lee and Young-Sun Min and Inryul Lee and In-Mo Kim and Sung-Hoon Kim and Dongkyu Yoon and KiSeung Kim and Youngdon Choi and Moosung Kim and Hyunggon Kim and Pansuk Kwak and Jeong-Don Ihm and Dae-Seok Byeon and Jin-Yub Lee and Ki-Tae Park and Kyehyun Kyung},
  journal={2017 IEEE International Solid-State Circuits Conference (ISSCC)},
  • Chulbum Kim, Ji-Ho Cho, +41 authors K. Kyung
  • Published 1 February 2017
  • Engineering, Computer Science
  • 2017 IEEE International Solid-State Circuits Conference (ISSCC)
The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has… 
A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput
This paper proposes a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput, which achieves a 5.63Gb/mm2 areal density, which is a 41.5% improvement as compared to a 3b/ cell Nander Flash memory in the same 3D-NAND technology.
A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism
The proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.
A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications
To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed and shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.
Three-Dimensional nand Flash for Vector–Matrix Multiplication
  • Panni Wang, F. Xu, +4 authors Shimeng Yu
  • Computer Science
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2019
This brief proposes using the 3-D vertical channel NAND array architecture to implement the vector–matrix multiplication (VMM) with for the first time, based on the array-level SPICE simulation, and the bias condition including the selector layer and the unselected layers is optimized to achieve high computation accuracy.
Architectural and Integration Options for 3D NAND Flash Memories
Several 3D NAND Flash memory technologies are exposed, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features.
GSSA: A Resource Allocation Scheme Customized for 3D NAND SSDs
GSSA (Generalized and Specialized Scramble Allocation), a novel written-data allocation scheme in SSD firmware, is proposed and evaluated, which considers both various 3D NAND program operations and the internal 3DNAND flash architecture.
Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory
This work develops a novel reprogramming scheme for TLCs in 3D NAND SSD, such that a cell can be programmed and reprogrammed several times before it is erased, which can reduce the frequency of erases, improve the speed of programming, and increase the amount of bits written in a cell per program/erase cycle.
PEN: Design and Evaluation of Partial-Erase for 3D NAND-Based High Density SSDs
This paper introduces PEN, an architecture-level mechanism that enables partial-erase of flash blocks and discusses how one can build a custom garbage collector for two types of flash translation layers (FTLs), namely, blocklevel FTL and hybrid FTL.
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time
An NVMe SSD controller is introduced which leverages the advantages of the low-latency NAND and enables the reduction of total memory access time, thereby minimizing overall system latency.
Array Architectures for 3-D NAND Flash Memories
3-D NAND Flash memories and the related integration challenges are discussed with the aid of several bird’s-eye views, and future scaling trends will be presented.


7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers
Cutting mold height increases resistance and capacitance for WLs due to the thinner layers being used and channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation.
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming
As a new 3D memory device with lower manufacturing cost and superior device scalability, the chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications such as mobile and personal computer.
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate
The previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension, so 3D-stacking technology has been developed.
Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory
Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.
Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory
Over erasure, charge gain in the low Vt state, and charge loss in the high Vt state are found to be the most severe reliability issues in a localized trapping storage flash memory cell. In this