100Gb/s ethernet chipsets in 65nm CMOS technology

@article{Jiang2013100GbsEC,
  title={100Gb/s ethernet chipsets in 65nm CMOS technology},
  author={Jhih-Yu Jiang and Ping-Chuan Chiang and Hao-Wei Hung and Chen-Lun Lin and Ty Yoon and Jri Lee},
  journal={2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers},
  year={2013},
  pages={120-121}
}
This paper presents a complete design of 100GbE chipsets including gearbox TX/RX, LDD and TIA/LA arrays. Figure 7.3.1 shows the architecture, where 10×10Gb/s input data is serialized into 4×25Gb/s bit stream by a 10:4 serializer (i.e., gearbox TX). A 4-element LDD array subsequently drives 4 laser diodes, emitting 850nm light into 4 multimode fibers (MMFs). After traveling over 100m, these optical signals are captured and transformed into electrical domain by means of photo diodes (PDs) and a… CONTINUE READING
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