10-GS/s track and hold circuit in 28 nm CMOS

Abstract

This paper presents the design and characterization of a 10 GS/s track and hold amplifier (THA). The circuit was fabricated in a 28 nm CMOS technology. It is based on a switched capacitor approach. At a sampling rate of 10 GS/s, the total harmonic distortion is -38dBc with a 3.75 GHz input signal. The chip includes an active balun and buffer stages for the… (More)

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Cite this paper

@article{Tretter201310GSsTA, title={10-GS/s track and hold circuit in 28 nm CMOS}, author={Gregor Tretter and David Fritsche and C. Carta and Frank Ellinger}, journal={2013 International Semiconductor Conference Dresden - Grenoble (ISCDG)}, year={2013}, pages={1-3} }