1.56 GHz On-chip Resonant Clocking in 130nm CMOS

@article{Hansson2006156GO,
  title={1.56 GHz On-chip Resonant Clocking in 130nm CMOS},
  author={Martin Hansson and Behzad Mesgarzadeh and Atila Alvandpour},
  journal={IEEE Custom Integrated Circuits Conference 2006},
  year={2006},
  pages={241-244}
}
This paper describes a successful experiment of 1.56-GHz on-chip LC-tank resonant clock oscillator, which directly drives 2times896 flip-flops, without intermediate buffers. Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip. Furthermore, clock jitter measurements show a worst-case… CONTINUE READING

Figures, Results, and Topics from this paper.

Key Quantitative Results

  • Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip.
  • Detailed measurements show that the resonant clocking results in 57 % lower clock power and 20 % lower total chip power, compared to the conventional clocking implemented in the same test-chip.
  • IEEE 241P-10-1 50 % reduction of the worst-case peak-to-peak jitter to 14.5 ps.
  • 11 shows the peak-to-peak and rms jitter measurements for data activities from 0 % to 80 % with an average clock frequency of 1.56 GHz, and with all flip-flops being fed with the same data-signal (worst-case).
  • Furthermore, the implemented oscillator incorporates an optional jitter suppression technique based on injection locking, which enables 50 % reduction of the worst-case peak-to-peak jitter down to 14.5 ps.

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