1.0-/spl mu/m n-Well CMOS/Bipolar Technology

  title={1.0-/spl mu/m n-Well CMOS/Bipolar Technology},
  author={H. Momose and H. Shibata and S. Saitoh and J. Miyamoto and K. Kanzaki and S. Kohyama},
  journal={IEEE Journal of Solid-State Circuits},
High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer… Expand
8 Citations
A high-performance bipolar/CMOS process-CIT2
A novel self-aligned bipolar/CMOS process called Collector Implanted Technology 2 (CIT2) with 1.5- mu m optical lithography has been developed. LSI chips fabricated in standard bipolar technologiesExpand
A high‐speed SRAM using BICMOS technology
To realize a large-capacity, high-speed ECL-compatible SRAM with an access time comparable to that of bipolar ECL RAMs, we have investigated a circuit configuration and optimizing method for SRAMsExpand
U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ) operation
Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the loadExpand
BiCMOS: technology and circuit design
Abstract In this paper, the state-of-the-art of combined bipolar/CMOS (BiCMOS) technologies and circuit techniques is described. Examples of advanced BiCMOS technologies for various applications willExpand
BiCMOS circuit technology for a high speed SRAM
A high speed and low power decoder with bipolar logic circuits and a high speed BiCMOS multiplexer with an emitter follower for the data line driver are proposed. Expand
BiCMOS—Circuits and Technology
The compatibility of present day VLSI CMOS and bipolar technologies is brought out and orientations necessary for optimization of devices and circuits involved are discussed. Expand
Symbolic Layout for Bipolar and MOS VLSI
A novel symbolic design technique which addresses both bipolar and MOS technologies is described, which allows the designer to symbolically layout nMOS, CMOS, and bipolar circuit structures. Expand
Technology compatibility and circuit complementarity of BIMOS
Recent developments in circuits and technology have underlined the importance of mixing technologies and circuit concepts in metal-oxide-semiconductor (MOS) and bipolar systems. This report is aimedExpand


A high-speed 64K CMOS RAM with bipolar sense amplifiers
A TTL-compatible 64K static RAM with CMOS-bipolar circuitry has been developed using a 1.2-/spl mu/m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mWExpand
High Performance 1.0 μm N-Well CMOS/Bipolar Technology
For achieving high performance VLSI's in logic and memory applications, CMOS becomes the dominant technology due to its very low power capability. As a 1.0 pμm level CMOS technology, it is quiteExpand
A merged CMOS/bipolar VLSI process
Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOSExpand
Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor
The LDD structure, where narrow, self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thusExpand
Directions in CMOS technology
This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and processExpand
A 28ns CMOS SRAM with bipolar sense amplifiers
This report will discuss a 64K×1 SRAM with bipolar sense amplifiers, utilizing both CMOS and bipolar devices with double poly 1.2μm MoSi processing. The SRAM typically accesses in 28ns and has a 20nAExpand
An ECL compatible 4K CMOS RAM
  • E. Hudson, S. Smith
  • Computer Science
  • 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 1982
A 4K×1 ECL compatible static RAM using a HMOSII/CMOS process and speed-optimized CMOS circuits to meet specifications of the ECL 10K logic family is discussed. Expand
A high-speed low-power Hi-CMOS 4K static RAM
A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realizedExpand
KanzakI, and S. well CMOS/bipolar technology for VLSI
  • Feb.,
  • 1978