1.0-/spl mu/m n-Well CMOS/Bipolar Technology

@article{Momose198510splMN,
  title={1.0-/spl mu/m n-Well CMOS/Bipolar Technology},
  author={H. Momose and H. Shibata and S. Saitoh and J. Miyamoto and K. Kanzaki and S. Kohyama},
  journal={IEEE Journal of Solid-State Circuits},
  year={1985},
  volume={20},
  pages={137-143}
}
High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer… Expand
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