1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

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@inproceedings{Moon200912V15, title={1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture}, author={Yongsam Moon and Yong-Ho Cho and Hyun-Bae Lee and Byung-Hoon Jeong and Seok-Hun Hyun and Byungchul Kim and In-Chul Jeong and Seong-Young Seo and Junho Shin and Seok-Woo Choi and Ho-Sung Song and Jung-Hwan Choi and Kyehyun Kyung and Young-Hyun Jun and Kinam Kim}, booktitle={ISSCC}, year={2009} }