1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography

@article{Hunter19791M,
  title={1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography},
  author={W. Hunter and L. Ephrath and W. Grobman and C. Osburn and B. Crowder and A. Cramer and H. Luhn},
  journal={IEEE Journal of Solid-State Circuits},
  year={1979},
  volume={14},
  pages={275-281}
}
For pt. IV see ibid., vol.SC14, no.2, p.268 (1979). An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 /spl mu/m, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations… Expand

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Luhn graduated from the Carl-DuisbergSchule in Wuppertal, West Germany, in 1951, and studied business administration in Remscheid, Germany
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