0.5 V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process

@article{Ichihashi200505VA,
  title={0.5 V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process},
  author={Mikio Ichihashi and Hiroyuki Toda and Yaomi Itoh and Kazuhiro Ishibashi},
  journal={Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.},
  year={2005},
  pages={366-369}
}
Asymmetric three-Tr. cell (ATC) DRAM which has one P-and two N-MOS transistors for one unit cell is proposed with "forced feedback sense amplifier" and "write echo refresh". Memory array of ATC DRAM operates at 0.5V and use only logic process with no additional process. A test chip on 90 nm technology dissipates 180 /spl mu/A in refresh current at 1 /spl mu/s cycle refresh on 1Mb with SG mode. 
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