0.5 V SOI CMOS pass-gate logic

@article{Fuse199605VS,
  title={0.5 V SOI CMOS pass-gate logic},
  author={Takao Fuse and Yukihito Oowaki and Mina Terauchi and Shigeyoshi Watanabe and Maiko Yoshimi and Katsuhiro Ohuchi and Jun-Ichi Matsunaga},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  year={1996},
  pages={88-89}
}
Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest… CONTINUE READING
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