0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme

@article{Moriwaki201104VSW,
  title={0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme},
  author={Shinichi Moriwaki and Atsushi Kawasumi and Toshikazu Suzuki and Takayasu Sakurai and Shinji Miyano},
  journal={2011 IEEE Custom Integrated Circuits Conference (CICC)},
  year={2011},
  pages={1-4}
}
128kbit SRAM with charge share hierarchical bit line scheme has been fabricated in 65nm foundry technology. By transferring the data between local bit lines and global bit lines with charge sharing, the variation of bit line swing which causes wasted power consumption in low voltage operation has been suppressed. 3.3µw/MHz of power consumption at 0.4V is achieved. 

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