0.4-µm gate-length devices fabricated by contrast-enhanced lithography

@article{Griffing198304181mGD,
  title={0.4-µm gate-length devices fabricated by contrast-enhanced lithography},
  author={B. F. Griffing and P N West and B. R. Heath},
  journal={IEEE Electron Device Letters},
  year={1983},
  volume={4},
  pages={317-320}
}
This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is… CONTINUE READING