0.25 µm CMOS technology using P+polysilicon gate PMOSFET

@article{Kasai1987025C,
  title={0.25 \&\#181;m CMOS technology using P+polysilicon gate PMOSFET},
  author={N. Kasai and N. Endo and H. Kitajima},
  journal={1987 International Electron Devices Meeting},
  year={1987},
  pages={367-370}
}
A 0.25 µm-channel CMOS Technology, in addition to a latchup-free 0.25 µm isolation technique, has been developed, using p+poly-Si gate pMOSFET. The p+poly-Si gate pMOSFET with shallow source/drain junctions, which has symmetric impurity profile to an n+poly-Si gate nMOSFET, is optimized by using a low energy BF2+implant, combined with a low temperature furnace annealing, followed by a rapid thermal annealing. A short channel effect for both nMOSFET and pMOSFET is reduced, by achieving the… Expand
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References

Design methodology for deep submicron CMOS
A design methodology for optimizing deep submicron CMOS devices is proposed, where gate oxide thickness Toxand supply voltage Vddare the main parameters. An operational region where all theExpand