0.25 µm CMOS technology using P+polysilicon gate PMOSFET

  title={0.25 \&\#181;m CMOS technology using P+polysilicon gate PMOSFET},
  author={N. Kasai and N. Endo and H. Kitajima},
  journal={1987 International Electron Devices Meeting},
A 0.25 µm-channel CMOS Technology, in addition to a latchup-free 0.25 µm isolation technique, has been developed, using p+poly-Si gate pMOSFET. The p+poly-Si gate pMOSFET with shallow source/drain junctions, which has symmetric impurity profile to an n+poly-Si gate nMOSFET, is optimized by using a low energy BF2+implant, combined with a low temperature furnace annealing, followed by a rapid thermal annealing. A short channel effect for both nMOSFET and pMOSFET is reduced, by achieving the… Expand
4 Citations
High-performance subquarter-micrometer gate CMOS technology
A single phosphorous-doped poly(n/sup +/)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltagesExpand
HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter
HSST/BiCMOS technology has been developed by merging a novel 0.3 mu m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 mu mExpand
Evolution of the MOS transistor-from conception to VLSI
Historical developments of the metal-oxide-semiconductor field-effect transistor (MOSFET) during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivityExpand
Challenges to manufacturing submicron, ultra-large scale integrated circuits
  • R. Fair
  • Engineering, Materials Science
  • 1990
It is argued that the cost of manufacturing submicron, ultra-large-scale integration (ULSI) integrated circuits (ICs) (which is scaling upward at least in inverse proportion to the downward scalingExpand


Design methodology for deep submicron CMOS
A design methodology for optimizing deep submicron CMOS devices is proposed, where gate oxide thickness Toxand supply voltage Vddare the main parameters. An operational region where all theExpand