Corpus ID: 27354259

` 4-Bit Fast Adder Design : Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuits

@inproceedings{Uma20114F,
  title={` 4-Bit Fast Adder Design : Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuits},
  author={R. Uma},
  year={2011}
}
  • R. Uma
  • Published 2011
  • Dynamic logic families offer good performance over traditional CMOS logic. This is due to the comparatively high noise margins coupled with the ease of implementation. The main drawbacks of dynamic logic circuits are lack of design automation, charge sharing, feedthrough, charge leakage, singleevent upsets, etc. But these draw backs can be eliminated using domino and NORA circuits but still lacks in the application of clock distribution grid and routing to dynamic gates that presents a problem… CONTINUE READING
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