<formula formulatype="inline"><tex Notation="TeX">${\rm SPICE}^2$</tex></formula>: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA

Abstract

Spatial processing of sparse, irregular, double-precision floating-point computation using a single field-programmable gate array (FPGA) enables up to an order of magnitude speedup (mean 2.8&#x00D7; speedup) over a conventional microprocessor for the SPICE circuit simulator. We develop a parallel, FPGA-based, heterogeneous architecture customized for… (More)

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Cite this paper

@article{Kapre2012formulaFN, title={\$\{\rm SPICE\}^2\$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA}, author={Nachiket Kapre and A Dehon}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2012}, volume={31}, pages={9-22} }