/spl times/pipes Lite: a synthesis oriented design library for networks on chips

@article{Stergiou2005splTL,
  title={/spl times/pipes Lite: a synthesis oriented design library for networks on chips},
  author={Stergios Stergiou and Federico Angiolini and Salvatore Carta and Luigi Raffo and Davide Bertozzi and Giovanni De Micheli},
  journal={Design, Automation and Test in Europe},
  year={2005},
  pages={1188-1193 Vol. 2}
}
The limited scalability of current bus topologies for Systems on Chips (SoCs) dictates the adoption of Networks on Chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While highly parametric, fully synthesizeable (soft) NoC building blocks appear as a good match for heterogeneous MPSoC architectures, the impact of instantiation-time flexibility on performance, power and… CONTINUE READING

References

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×pipes : a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs

  • M. Dall’Osso et. al
  • 2003
Highly Influential
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