Corpus ID: 16016048

"Power Reduction in CMOS Technology by using Tri-State Buffer and Clock Gating"

@inproceedings{Jaiswal2014PowerRI,
  title={"Power Reduction in CMOS Technology by using Tri-State Buffer and Clock Gating"},
  author={R. Jaiswal and R. Paul and Vikas Mahto and O. P. Jindal},
  year={2014}
}
1853 ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET  Abstract— In this research paper we have implemented different type of clock gating techniques and proposed technique to reduce power. All the techniques are performed at different technology with temperature, voltage and frequency variation and their Dynamic, static and total power has been computed, In this we are applying clock gating techniques on a 8 bit Arithmetic logical unit (ALU).here we had compared different clock gating… Expand

Figures, Tables, and Topics from this paper

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References

SHOWING 1-10 OF 24 REFERENCES
A clock gated flip-flop for low power applications in 90 nm CMOS
  • M. Shaker, M. Bayoumi
  • Engineering, Computer Science
  • 2011 IEEE International Symposium of Circuits and Systems (ISCAS)
  • 2011
TLDR
Simulations with the inclusion of parasitics have shown the effectiveness of the new approach on power consumption and transistor count. Expand
Activity aware clock gated storage element design
TLDR
A new clock gating methodology for low-power clocked storage element design is presented, which removes unnecessary clock toggling and reduces capacitive loading, which both lead to reduced dynamic power and reduced design complexity. Expand
The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating
  • S. Wimer, I. Koren
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2012
TLDR
A probabilistic model of the clock gating network is developed that allows for the expected power savings and the implied overhead and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. Expand
Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes
TLDR
Some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology and improved active-driven optimized bus-specific clock gating (OBSC) is proposed in the laboratory. Expand
Clock gating — A power optimizing technique for VLSI circuits
TLDR
The work in this paper investigates the various clock gating techniques that can be used to optimise power in VLSI circuits at RTL level and various issues involved while applying this power optimization techniques atRTL level. Expand
Low power clock gates optimization for clock tree distribution
  • Siong Kiong Teng, N. Soin
  • Computer Science
  • 2010 11th International Symposium on Quality Electronic Design (ISQED)
  • 2010
TLDR
This paper presents a new physical clock gates optimization technique using splitting and merging algorithm that works on both single level and multiple levels clock gating design and shows improvement on overall clock tree power. Expand
Power Reduction of ITC'99-b01 Benchmark Circuit Using Clock Gating Technique
This paper, deals with Latch Free Clock Gating technique for reduction of clock power and dynamic power consumption in ITC'99 bo1 Benchmark circuit and we have compared power reduction at differentExpand
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs
TLDR
A new structural clock-gating technique based on internal partial reconfiguration and topological modifications related to the clock routing resources is developed, which is not intrusive, and presents a very limited cost in term of area overhead. Expand
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
  • S. Wimer, I. Koren
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2014
TLDR
Data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%-20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies. Expand
Using clock gating technique for energy reduction in portable computers
  • D. R. Sulaiman
  • Computer Science
  • 2008 International Conference on Computer and Communication Engineering
  • 2008
TLDR
A hardware design of the clock gating technique is presented, which enables the CPU to reduce the supply voltage accompanied with the clock frequency, based on its workload variation, which leads to a possible reduction in power requirements. Expand
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