Corpus ID: 14498125

. " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout

@inproceedings{RohleischS,
  title={. " Sis: a System for Sequential Circuit Synthesis, " Report M92/41, A) Shallow Reconvergant Fanout A) Deep Reconvergant Fanout},
  author={B Rohleisch and A. Kolbl and B. Wurth and K Roy and R Rudell and H Savoj and M Schulz and E. Auth and E Sentovich and K. Singh and C. Moon and H. Savoj and R. Brayton and A. Sangiovanni-Vintentelli and Sequential and Shen and Ayut Ghosh and S. Devadas and K. Keutzer and C. Tsui and M. Pedram and Cheng-Hsi Chen and A. Despain and Power and S. Vrudhula and H. Y. Xie and J A Waicukauski and E. Eichelberger and D. Forlenza and E. Lindbloom and T. McCarthy and Fault Simula and Wang and G D Hachtel and R. Jacoby and P. Moceyunas and J Hong and R. Cain and D. Ostapko and Kunz and D. Pradhan and B Lin and A. Newton and H. De and Liu and C. Svensson and A A Malik and A. Sangiovanni-Vincentelli and R Marculescu and D. Marculescu and D Marculescu and R. Marculescu and Muroga and Y. Kambayashi and H. Lai and J. N. Culliney and R K Brayton and G. Hachtel and Multi-Level and R Brayton and C. McMullen and Minimization Logic and Algo and A Chandrakasan and M. Potkonjak and J. Rabaey and R. Brodersen and Hyper and S. C. Chang and K. T. Cheng and N. Woo and M. Marek-Sadowska and Cheng and L. Entrena and Multi and Coudert and C. Berthet and J. Madre and U. Berkeley and J. Alidina and S. Monteiro and A. Devadas and M. Ghosh and Papaefthymiou and Bartlett and C. Morrison and R. Rudell and A. Wang}
}
Reducing power dissipation after technology mapping by structural transformations. Circuit activity based logic synthesis for low power reliable operations. " IEEE Advanced Automatic test pattern generation and redundancy identification techniques. circuit design using synthesis and optimization. On average power dissipation and random pattern testability of CMOS combinational logic networks. Low power state assignment targeting two-and multi-level logic implementations. Efficient estimation of… Expand
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