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- Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
- ASP-DAC 2004: Asia and South Pacific Design…
- 2004

In this paper, we present an efficient method to budget on-chip decoupling capacitors (decaps) to optimize power delivery networks in an area efficient way. Our algorithm is based on an efficient gradient-based non-linear programming method for searching the solution. Our contributions are an efficient gradient computation method (time-domain merged adjoint… (More)

- Zuying Luo, Xiaowei Li, Xiaowei Li, Shiyuan Yang, Yinghua Min
- Asian Test Symposium
- 2002

- Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
- ISCAS
- 2004

This paper proposes a new simulation algorithm for analyzing large power distribution networks, modeled as linear RLC circuits, based on a novel partial random walk concept. The random walk simulation method has been shown to be an efficient way to solve for a small number of nodes in a lager power distribution network [6], but the algorithm becomes… (More)

- Zuying Luo, Yici Cai, +4 authors Jingjing Fu
- Science in China Series F: Information Sciences
- 2006

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup… (More)

- Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
- Proceedings of the ASP-DAC 2005. Asia and South…
- 2005

In today's power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink below 20Å. As a result, decaps will become leaky due to the gate leakage from CMOS devices. In this… (More)

- Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
- ISQED
- 2004

* This work is supported by the National Natural Science Foundation of China 60176016 and 90307017 and by the Senate Research funds of the University of California. Abstract This paper presents an efficient method to analyze power distribution networks in the time-domain. Instead of directly analyzing the integration approximated power/ground networks at… (More)

- Zuying Luo
- ACM Great Lakes Symposium on VLSI
- 2006

In this work, we modify the Alpha-Power Law to accurately simulate BSIM3-70nm gate delay on transistor level. Combined with efficient power analysis methods, we develop one transistor-level simulator to efficient estimate performance and power for CMOS gates consisting of heterogeneous transistors. Furthermore, we propose a novel transistor-level… (More)

- Yongjun Xu, Zuying Luo, Xiaowei Li
- ISCAS
- 2004

- Wei Zhao, Zuying Luo, Jeffrey Fan, S.X.-D. Tan
- 2008 International Conference on Embedded…
- 2008

Motion estimation (ME) is one of the bottlenecks in terms of the computational cost in a video encoder system. In this paper, we present a cost-effective method to calculate the "Vector Edge" of the current frame. We store all the vectors' information within a frame and put them in the Laplacian of Gaussian edge detection operator. It is similar to the… (More)

This paper proposes a new simulation algorithm for analyzing large power distribution networks, modeled as linear RLC circuits, based on a novel partial random walk concept. The random walk simulation method has been shown to be an efficient way to solve for voltages of small number of nodes in a large power distribution network [2], but the algorithm… (More)